NXP Semiconductors
PCA9626
24-bit Fm+ I 2 C-bus 100 mA 40 V LED driver
[2]
Each bit must be limited to a maximum of 100 mA and the total package limited to 2400 mA due to internal busing limits.
14. Dynamic characteristics
Table 19.
Dynamic characteristics
Symbol
Parameter
Conditions
Standard-mode
Fast-mode
Fast-mode
Unit
I 2 C-bus
I 2 C-bus
Plus I 2 C-bus
Min
Max
Min
Max
Min
Max
f SCL
t BUF
SCL clock frequency
bus free time
0
4.7
100
-
0
1.3
400
-
0
0.5
1000
-
kHz
? s
between a STOP and
START condition
t HD;STA
hold time (repeated)
4.0
-
0.6
-
0.26
-
? s
START condition
t SU;STA
set-up time for a
4.7
-
0.6
-
0.26
-
? s
repeated START
condition
t SU;STO
set-up time for STOP
4.0
-
0.6
-
0.26
-
? s
condition
t HD;DAT
data hold time
0
-
0
-
0
-
ns
t VD;ACK
data valid
[1]
0.3
3.45
0.1
0.9
0.05
0.45
? s
acknowledge time
t VD;DAT
t SU;DAT
t LOW
data valid time
data set-up time
LOW period of the
[2]
0.3
250
4.7
3.45
-
-
0.1
100
1.3
0.9
-
-
0.05
50
0.5
0.45
-
-
? s
ns
? s
SCL clock
t HIGH
HIGH period of the
4.0
-
0.6
-
0.26
-
? s
SCL clock
t f
fall time of both SDA
[3][4]
-
300
20 + 0.1C b [5]
300
-
120
ns
and SCL signals
t r
rise time of both SDA
-
1000
20 + 0.1C b [5]
300
-
120
ns
and SCL signals
t SP
pulse width of spikes
[6]
-
50
-
50
-
50
ns
that must be
suppressed by the
input filter
Output propagation delay
t PLH
LOW to HIGH
OE to LEDn;
-
-
-
-
-
150
ns
propagation delay
MODE2[1:0] = 01
t PHL
HIGH to LOW
OE to LEDn;
-
-
-
-
-
150
ns
propagation delay
MODE2[1:0] = 01
PCA9626
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 September 2012
? NXP B.V. 2012. All rights reserved.
36 of 47
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